Advanced microfabrication and nanofabrication patterning techniques enable the fabrication and assembly of structures on substrate surfaces. The spectrum of available patterning techniques includes photolithography, soft lithography (e.g., contact printing), electron beam direct writing, and photoablation patterning methods. This suite of available patterning techniques is compatible with a wide range of substrates and deposition materials, including high quality semiconductors, dielectrics and conducting materials, and is compatible with processing a useful range of substrate materials, morphologies, and sizes. In combination with state of the art resist processing and materials deposition techniques, advanced patterning techniques provide a high degree of deterministic control over the physical dimensions and spatial arrangements of patterned structures having dimensions ranging from a few nanometers to thousands of microns.
Given the precision and versatility provided by these methods, advanced substrate patterning techniques provide a commercially viable fabrication platform for accessing a range of useful functional structures and devices. Microfabrication and nanofabrication patterning techniques have been developed that are capable of accessing complex device and device array geometries, including three-dimensional multilayer thin film structures and devices. These techniques currently play a central role in most semiconductor-based technologies including, but not limited to, the manufacture of integrated electronic circuits, memory devices, sensing systems, photovoltaic systems and other microelectronic devices. Furthermore, advanced substrate patterning techniques also provide an effective fabrication pathway for making and integrating nanometer and/or micron scale structures for active and passive elements in micro- and nano-electromechanical systems (MEMS & NEMS) and micro- and nano-fluidic systems.
Motivation for the continued improvement of microfabrication and nanofabrication patterning technology originates, at least in part, from demand for a new class of very high performance densely integrated electronic systems. Developments in advanced patterning techniques, such as deep ultraviolet photolithography, electron beam writing and X-ray lithography methods, have extended the applicability of these techniques for generating patterns of structures and features with dimensions as small as tens of nanometers. These advances continue to enhance device component densities accessible by these techniques. Critical to the continued development and commercialization of this field, however, is the development of low cost microfabrication and nanofabrication processing strategies for making and integrating nanosized and microsized structures having complex three dimensional shapes necessary for device components in high speed integrated electronic systems, such as RF, wireless and high power devices.
Field effect transistors (FETs) are an example of a class of electronic device for which advances in microfabrication techniques continue to play a significant role in accessing important performance benefits. These devices include traditional silicon based FETs and FETs employing III-V compound semiconductors as active materials commonly called high electron mobility transistors (HEMTs). FETs comprise a semiconductor element and three primary electrodes: source, drain and gate electrodes. An electric field established by application of a voltage to the gate electrode is used in these devices to control the shape, and hence conductivity, of a channel in the semiconductor element. Specifically, the voltage applied between gate and source terminals modulates the current passing through the semiconductor provided between sources and drain electrodes. A number of useful FET designs have been developed over the years, including Metal-oxide-Semiconductor Field-Effect Transistors (MOSFET), Metal-Semiconductor-Field-Effect Transistors (MESFET), and Junction Field-Effect Transistor (JFET). FETs are used in a wide range of integrated electronic devices for two primary device functionalities; namely, for switching and for amplifying of current signals. FET devices are also commonly used as voltage-controlled resistors.
A design strategy that has been demonstrated particularly attractive for accessing FETs capable of high switching speeds has been the development of gate electrodes having non-uniform cross-sectional geometries. T-gate electrodes, for example, have been developed having a T-shaped cross-sectional profile including a narrow stem portion and a wider top portion. The narrow stem portion establishes electrical contact with the FET semiconductor channel, thereby defining a small gate length for accessing useful device capacitance and instrinsic transconductance. This geometry allows for submicron gate lengths, which provide reduced gate capacitance and electron transit times. The wider top portion, on the other hand, provides a low resistance path to the stem, thereby minimizing net gate resistance. Accordingly, the T-shape geometry of T-gate electrodes provides a combination of electronic properties useful for enhancing device performance, such as switching speed. A variation of the T-gate electrode has also been developed wherein the wider top portion is offset toward the drain electrode. This electrode configuration, commonly referred to as a gamma-gate (or G-gate), further reduces the net gate to source capacitance and resistance, thereby enhancing device performance.
T-gate and G-gate electrode geometries are particularly attractive for a number of applications. First, T-gate and G-gate electrodes are commonly used in high performance HEMT device structures for important RF (Radio Frequency), High Power and Wireless Applications. Second, T-gate and G-gate electrodes are commonly incorporated into high power devices and multi-finger devices on gallium nitride substrates in the power electronics industry. Third, high frequency circuits using T-gates and G-gates are extremely popular with the telecommunications industry. For example, gallium arsenide based circuits now have more than 80% of the market share when it comes to chips used in cell phones.
There are several methods currently used for fabricating T-gate and G-gate structures for FETs and HEMTs. If the T-gates are manufactured for low volume production, for example, the two most popular methods are: (i) a Bi-Layer resist process, and (ii) a Tri-Layer resist process. U.S. Pat. Nos. 4,959,326, 5,155,053 and 5,053,348 provide examples of conventional methods for making T-gate electrodes using multilayer resist processing protocols. For large scale manufacture processing, T-gates are typically fabricated using two entirely independent lithographic steps. In these methods, the first lithographic step defines and patterns the stem, and the second lithographic step defines and patterns the tee-top of the T-gate structure.
The Bi-Layer resist process uses two photoresist materials: a first of low molecular weight resist and a second of high molecular weight resist. A first resist layer of high molecular weight is applied on the substrate undergoing processing, and a second resist layer of low molecular weight is subsequently applied on top of the first resist layer of high molecular weight. The resist stack of first and second layers is exposed to an electron beam in the case of electron beam lithography (EBL), or to deep ultraviolet electromagnetic radiation (DUV) in the case of DUV Lithography. After this exposure step the substrate is developed. The developer dissolves the exposed region (e.g., for a positive resist) of the first and second resist layers. In addition, the developer reacts chemically with the unexposed regions on the first and second resist layers, thereby dissolving them but at a much slower rate compared to dissolution of the exposed regions of the resist layers. The developer reacts faster with the resist of lower molecular weight than it reacts with the resist of higher molecular weight, thereby generating a recessed feature having a non-uniform cross section (e.g., narrower cross section in high molecular weight resist layer and wider cross section in the lower molecular weight resist layer). Upon deposition of an appropriate gate material(s), the narrow stem portion of the T-gate is formed in the lower, high molecular weight resist layer and the wider top portion is formed in the upper, low molecular weight resist layer because it has developed more than the lower layer high molecular weight resist layer.
In the case of a Tri-Layer process, the process is similar to that described above with the exception that a stack of three resists is used. All three layers can have different rates of chemical reaction with the developer thereby providing additional control on the cross-sectional geometry of the gate electrode. This process is currently used to fabricate complicated T-gate style gates, such as Mushroom Gates, to further lower resistance.
There are currently other more complicated processes of making T-gates and G-gates where multiple layers of different resist materials are used, different developers are used during processing and, optionally, the E-beam (or UV electromagnetic radiation) intensity is selectively varied for each resist layer depending on its molecular weight and chemical composition. In some processing methods, the E-beam (or UV electromagnetic radiation) intensity is also controlled as a function of distance as the beam scans.
The processing steps for gamma gates are similar to that of T-gates. Gamma Gates can be fabricated by making a judicious choice of resists and developers used and also by changing the E-Beam intensity as a function of distance in the direction of the beam scan.
Processing methods for making T-gates and G-gates using multiple resist stacks have several important disadvantages that impede full integration of this technology. First, use of multiple resists and multiple developers is very costly and labor intensive. This is largely because several separate resist deposition and development processing steps are involved, which increase net processing costs at an exponential rate. Second, use of multiple resist layers during processing inevitably results in intermixing of the applied resist layers, which can result in significant deviations in the cross-sectional geometry of the gate structure achieved. Third, the baking temperature required for a second resist layer might not be suitable for the layers of resist (e.g., first resist layer) already applied, which can severely affect the gate cross-sectional profile. Fourth, a developer intended for one resist layer can attack other resist layers, thereby degrading the profile of the structure. Fifth, the resist of highest molecular weight may not receive the desired radiant dose during exposure because of its position at the bottom of the resist stack. This can lead to problems in achieving a desired cross-sectional geometry upon development. In addition, a significant problem arises with the alignment of the stem with the tee-top when T-gates intended for large scale are manufactured via a two step lithographic process.
It will be appreciated from the foregoing that that there is currently a need for microfabrication and nanofabrication processing methods capable of making nanosized and microsized structures having selected non-uniform cross-sectional geometries. Processing methods are needed that are capable of generating structures providing T-gate and G-gate electrodes for high performance FETs and HEMTs. It will also be appreciated that a need exists for new methods of making T-gate and G-gate electrodes that are capable of high throughput and low cost production and integration into FET and HEMT systems.